1. Technical Field
The present invention relates generally to dynamic management and control of power and performance for an integrated circuit chip, and more specifically, to systems and methods for a power/performance monitoring and control unit that can improve instruction throughput and power management.
2. Description of the Related Art
Chip-level power dissipation limits constitute a fundamental design constraint in future high-performance microprocessors. In a multi-core processor, the chip-level performance targets are aggressive, and meeting the power budget at high performance levels presents a major design challenge. On-chip, dynamic power management is therefore a design feature that needs to be considered as an integral part of the overall architecture.
Several analysis have shown that clock-gating alone is not enough to meet the chip-level power budget for multi-core designs that could meet the chip-level performance requirements. Both average and maximum power need to be managed to remain within acceptable limits, dictated by power-related maintenance cost budgets and cooling/packaging solution cost limits.
Previous research has shown that individual techniques for dynamic management of power (be it of the active, passive or both), invariably have the following characteristics: (a) the average power savings is a strong function of the input workload; in fact in some cases, the net power savings may even be zero or negative; (b) depending on the technique, there is usually an associated performance penalty—either in terms of cycle time (frequency) or cycles per instruction (CPI); (c) there is an area overhead that is paid as a price for any expected power reduction; (d) there is no direct or easy way to bound the worst-case power that is consumed: usually, the only way is an empirical pre-silicon evaluation using an assumed worst-case workload.
As such, given conventional solutions to reduce power, it is clear that ideally, one would like to invoke a subset of these solutions, depending on the workload or the particular phase of the workload. This implies the need for some kind of a “monitor-and-control” facility that would sense the workload demand and microarchitectural activity and dynamically invoke particular mechanisms from within a full repertoire of architected techniques for power reduction and control.